Dual printhead controller architecture includes a master central processor capable of being interfaced with a first printhead. A slave central processor is capable of being interfaced with a second printhead. Data transfer means is operatively connected between the master central processor and the slave central processor to permit communication between the master and slave central processors. A host link is operatively connected to the master central processor to permit the master central processor to receive page data from a host processor. Ink cartridge quality assurance integrated circuitry is connected to the master central processor.