Invention Grant
- Patent Title: Method for electrically trimming an NVM reference cell
- Patent Title (中): 电动修整NVM参考单元的方法
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Application No.: US12130186Application Date: 2008-05-30
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Publication No.: US07782664B2Publication Date: 2010-08-24
- Inventor: Horacio P. Gasquet , Richard K. Eguchi , Peter J. Kuhn , Ronald J. Syzdek
- Applicant: Horacio P. Gasquet , Richard K. Eguchi , Peter J. Kuhn , Ronald J. Syzdek
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Kim-Marie Vo; Daniel D. Hill
- Main IPC: G11C11/34
- IPC: G11C11/34

Abstract:
An integrated circuit memory has a plurality of non-volatile memory cells and a reference cell. The reference cell provides a reference current for reading a selected memory cell of the plurality of non-volatile memory cells. A method comprises trimming the reference cell to a predetermined threshold voltage, wherein trimming the reference cell comprises biasing a control gate, a source terminal, a drain terminal, and a substrate terminal of the reference cell with a predetermined set of bias conditions, wherein in response to the predetermined set of bias conditions, the reference cell will gain or lose charge toward an asymptotic state of charge that no longer changes significantly after a predetermined operating time under the predetermined set of bias conditions. In addition, the integrated circuit memory is also configured to adjust the reference cell gate voltage to output a desired target current reference.
Public/Granted literature
- US20090296464A1 METHOD FOR ELECTRICALLY TRIMMING AN NVM REFERENCE CELL Public/Granted day:2009-12-03
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