A semiconductor memory device is capable of controlling a tRCD (RAS to CAS Delay) time regardless of an address input timing during a test operation of the semiconductor memory device. The semiconductor memory device includes a column address strobe pulse generator for generating a column address strobe pulse in response to a column command signal and a row address strobe pulse generator for receiving an active command signal or the column command signal to produce a row address strobe pulse in response to a test mode signal.