Invention Grant
- Patent Title: Semiconductor integrated circuit and memory checking method
- Patent Title (中): 半导体集成电路和存储器检查方法
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Application No.: US12053944Application Date: 2008-03-24
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Publication No.: US07782689B2Publication Date: 2010-08-24
- Inventor: Tokushi Yamaguchi , Hiroyuki Sekiguchi , Ryoji Shiota , Mitsuya Nakano
- Applicant: Tokushi Yamaguchi , Hiroyuki Sekiguchi , Ryoji Shiota , Mitsuya Nakano
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JPP.2007-103954 20070411
- Main IPC: G11C29/12
- IPC: G11C29/12

Abstract:
The semiconductor integrated circuit includes a memory for storing secret data, a memory BIST circuit for executing a memory. BIST, a first selector for switching between a path for a memory isolation test via an external terminal and a path from the memory BIST circuit, a second selector for switching between a path from the output of the first selector and a path from a normal circuit and having an output coupled to the memory, and a third selector for switching between a path from the output of the memory and a path for receiving a pseudo signal and receiving a check completion signal outputted from the memory BIST circuit as a selection signal. In this semiconductor integrated circuit, after the memory is initialized by executing the memory BIST, the memory can be accessed from the external terminal via the path for the memory isolation test.
Public/Granted literature
- US20080253208A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND MEMORY CHECKING METHOD Public/Granted day:2008-10-16
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