Invention Grant
- Patent Title: Semiconductor memory device having a word line activation circuit and/or a bit line activation circuit and a redundant word line activation circuit and/or a redundant bit line acitvation circuit
- Patent Title (中): 具有字线激活电路和/或位线激活电路和冗余字线激活电路和/或冗余位线启动电路的半导体存储器件
-
Application No.: US12258835Application Date: 2008-10-27
-
Publication No.: US07782706B2Publication Date: 2010-08-24
- Inventor: Yasushi Nishida
- Applicant: Yasushi Nishida
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2007-293513 20071112
- Main IPC: G11C8/10
- IPC: G11C8/10

Abstract:
A word line activation circuit having a temporary memory circuit for storing word line inactivation information for inactivating a word line of a defective memory cell, and an inactivation address sensing circuit for determining whether or not a redundant memory cell is to be used in accordance with the word line inactivation information and an address specification signal is provided for each of word lines. When the inactivation address sensing circuit determines that the redundant memory cell is to be used, a redundant word line is activated by a redundant word line activation circuit.
Public/Granted literature
- US20090122624A1 SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2009-05-14
Information query