A semiconductor memory device and method thereof are provided. The example semiconductor memory device may include a memory cell array including a plurality of memory cells, an expected data generating unit receiving a plurality of initial expected data through at least one address pad during a memory operation and generating a plurality of expected data based on the plurality of initial expected data, the at least one address pad being separate from a data input/output pad and a parallel bit test circuit generating test result data based on a plurality of read data and the plurality of expected data.