Invention Grant
US07784020B2 Semiconductor circuit pattern design method for manufacturing semiconductor device or liquid crystal display device
失效
用于制造半导体器件或液晶显示器件的半导体电路图案设计方法
- Patent Title: Semiconductor circuit pattern design method for manufacturing semiconductor device or liquid crystal display device
- Patent Title (中): 用于制造半导体器件或液晶显示器件的半导体电路图案设计方法
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Application No.: US11429077Application Date: 2006-05-08
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Publication No.: US07784020B2Publication Date: 2010-08-24
- Inventor: Kyoko Izuha , Fumihiro Minami , Toshiaki Ueda , Ryuji Ogawa , Satoshi Tanaka
- Applicant: Kyoko Izuha , Fumihiro Minami , Toshiaki Ueda , Ryuji Ogawa , Satoshi Tanaka
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2005-137423 20050510
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A semiconductor circuit pattern design method includes the following operations. A design pattern is created by placing a plurality of cells in each functional block as a unit of the semiconductor circuit and executing routing among the plurality of placed cells. Mask pattern data based on the design pattern is created. A predictive pattern to be formed on the substrate by the mask pattern data is predicted. A difference amount between the predictive pattern and a target pattern to be formed on the substrate by the mask pattern data is checked. The difference amount is compared with a predetermined allowable variation amount. If the difference amount is larger than the allowable variation amount in the comparison, at least one of placement and routing of the cells in the design pattern corresponding to the mask pattern data used to predict the predictive pattern is corrected.
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