Invention Grant
US07786569B2 Semiconductor device using wiring substrate having a wiring structure reducing wiring disconnection
失效
使用具有减少布线断线的布线结构的布线基板的半导体装置
- Patent Title: Semiconductor device using wiring substrate having a wiring structure reducing wiring disconnection
- Patent Title (中): 使用具有减少布线断线的布线结构的布线基板的半导体装置
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Application No.: US12013422Application Date: 2008-01-12
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Publication No.: US07786569B2Publication Date: 2010-08-31
- Inventor: Kazuyuki Nakagawa
- Applicant: Kazuyuki Nakagawa
- Applicant Address: JP Tokyo
- Assignee: Renesas Technology Corp.
- Current Assignee: Renesas Technology Corp.
- Current Assignee Address: JP Tokyo
- Agency: Miles & Stockbridge P.C.
- Priority: JP2007-010262 20070119
- Main IPC: H01L23/053
- IPC: H01L23/053 ; H01L23/12

Abstract:
The semiconductor device concerning the present invention has a wiring substrate, a semiconductor chip, under-filling resin, a reinforcement ring, a heat spreader, a power supply pattern and a wiring layer under surface via land which are formed on the wiring substrate and spaced out by a clearance region, an insulating film, a wiring layer via land, a via, and a wiring which is formed on the insulating film, passes over the clearance region, and connects the wiring layer via land to the semiconductor chip. The wiring layer via land is formed between the semiconductor chip and the reinforcement ring, and within a region of a 1 mm width from the extension line of the diagonal line of the semiconductor chip. The angle of the lead-out direction of the wiring from a wiring layer via land to the extension line of the diagonal line of the semiconductor chip is 20° or more.
Public/Granted literature
- US20080174004A1 SEMICONDUCTOR DEVICE USING WIRING SUBSTRATE HAVING A WIRING STRUCTURE REDUCING WIRING DISCONNECTION Public/Granted day:2008-07-24
Information query
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