Invention Grant
US07786761B2 Output buffer device 有权
输出缓冲器

Output buffer device
Abstract:
A controlling output buffer slew rate method and an output buffer circuit for a memory device is provided. The output buffer include an output stage formed by a PMOS transistor and a NMOS transistor electrically connected in series, a pre-driver for respectively controlling each gate terminal of the PMOS transistor and the NMOS transistor in order to bring these transistors to the turning-on threshold, a first wire, for transmitting a pull-up signal, coupled between the output stage and the pre-driver, and a second wire, for transmitting a pull-down signal, coupled between the output stage and the pre-driver. After a DATA signal transition (logic state is changed from “H” to “L” or “L” from to “H”), the PMOS or NMOS transistor is turned off first, and then the NMOS or PMOS transistor is turned on due to the time difference between the pull-up signal and the pull-down signal.
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