Invention Grant
- Patent Title: Error correcting processing device and error correcting processing method
- Patent Title (中): 纠错处理装置和纠错处理方法
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Application No.: US11523031Application Date: 2006-09-19
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Publication No.: US07788574B2Publication Date: 2010-08-31
- Inventor: Kenji Yoshida
- Applicant: Kenji Yoshida
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2005-332978 20051117
- Main IPC: H03M13/00
- IPC: H03M13/00

Abstract:
According to one embodiment, modulation processing to convert digital information sequences into a form that meets a request from a recording/reproducing system is performed on a digital information sequence and a dummy bit is added to the sequence, and furthermore, an error correcting parity bit sequence is added to the digital information sequence. If the added parity bit sequence does not correspond to a form that meets a request from the recording/reproducing system, a value of the dummy bit is changed and the parity bit sequence is replaced with a parity bit sequence that corresponds to the dummy bit of the changed value.
Public/Granted literature
- US20070124660A1 Error correcting processing device and error correcting processing method Public/Granted day:2007-05-31
Information query
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