Invention Grant
- Patent Title: Solder printing process to reduce void formation in a microvia
- Patent Title (中): 焊接印刷工艺以减少微孔中的空隙形成
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Application No.: US11975227Application Date: 2007-10-17
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Publication No.: US07789285B2Publication Date: 2010-09-07
- Inventor: Cheng Siew Tay , Pek Chew Tan , Swee Kian Cheng , Eng Hooi Yap
- Applicant: Cheng Siew Tay , Pek Chew Tan , Swee Kian Cheng , Eng Hooi Yap
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: B23K31/02
- IPC: B23K31/02 ; B05D5/12
Abstract:
In one embodiment, a method is provided. The method comprises filling a microvia formed in a bond pad with solder paste comprising solder balls of the first size; and coating the bond pad with solder paste comprising solder balls of the second size, wherein the second size is greater than the first size.
Public/Granted literature
- US20080099539A1 Solder printing process to reduce void formation in a microvia Public/Granted day:2008-05-01
Information query
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