Invention Grant
US07790500B2 Partially patterned lead frames and methods of making and using the same in semiconductor packaging
有权
部分图案化引线框架及其在半导体封装中的制造和使用方法
- Patent Title: Partially patterned lead frames and methods of making and using the same in semiconductor packaging
- Patent Title (中): 部分图案化引线框架及其在半导体封装中的制造和使用方法
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Application No.: US11877732Application Date: 2007-10-24
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Publication No.: US07790500B2Publication Date: 2010-09-07
- Inventor: Mary Jean Ramos , Anang Subagio , Lynn Simporios Guirit , Romarico Santos San Antonio
- Applicant: Mary Jean Ramos , Anang Subagio , Lynn Simporios Guirit , Romarico Santos San Antonio
- Applicant Address: MU Port Louis
- Assignee: Unisem (Mauritius) Holdings Limited
- Current Assignee: Unisem (Mauritius) Holdings Limited
- Current Assignee Address: MU Port Louis
- Agency: White & Case LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/495

Abstract:
A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging lead-count, wherein the method lends itself to better automation of the manufacturing line and improved quality and reliability of the packages produced therefrom. A major portion of the manufacturing process steps is performed with a partially patterned strip of metal formed into a web-like lead frame on one side so that the web-like lead frame is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation.
Public/Granted literature
- US20080258278A1 Partially patterned lead frames and methods of making and using the same in semiconductor packaging Public/Granted day:2008-10-23
Information query
IPC分类: