A manufacturing process for a chip package structure is provided. First, a patterned conductive layer having a plurality of first openings and a first patterned solder resist layer on the patterned conductive layer are provided. A second patterned solder resist layer is formed on the patterned conductive layer such that the first patterned solder resist layer and the second patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer. Chips are bonded onto the first patterned solder resist layer such that the first patterned solder resist layer is between the chips and the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires passing through the first openings. At least one molding compound is formed and the molding compound, the first patterned solder resist layer and the second patterned solder resist layer are separated.