Invention Grant
- Patent Title: Method of manufacturing semiconductor device
- Patent Title (中): 制造半导体器件的方法
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Application No.: US11854225Application Date: 2007-09-12
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Publication No.: US07790517B2Publication Date: 2010-09-07
- Inventor: Kazutaka Manabe , Eiji Kitamura
- Applicant: Kazutaka Manabe , Eiji Kitamura
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: Sughrue Mion, PLLC
- Priority: JP2006-279521 20061013
- Main IPC: H01L21/82
- IPC: H01L21/82 ; H01L21/336 ; H01L21/38 ; H01L21/22 ; H01L21/44

Abstract:
A method of manufacturing a semiconductor device forms an N− diffusion layer to be a source/drain region of a grooved transistor simultaneously with an N− diffusion layer of a channel region directly under a gate electrode of an antifuse element. The formation of the N− diffusion layer directly under the gate electrode of the antifuse element stabilizes electrical connection between the gate electrode and the source/drain diffusion region even during writing with a low write voltage.
Public/Granted literature
- US20080090363A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2008-04-17
Information query
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