Invention Grant
- Patent Title: Integration of strained Ge into advanced CMOS technology
- Patent Title (中): 将应变锗融入先进的CMOS技术
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Application No.: US12118689Application Date: 2008-05-10
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Publication No.: US07790538B2Publication Date: 2010-09-07
- Inventor: Huiling Shang , Meikei Ieong , Jack Oon Chu , Kathryn W. Guarini
- Applicant: Huiling Shang , Meikei Ieong , Jack Oon Chu , Kathryn W. Guarini
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent George Sai-Halasz; Louis J. Percello
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.
Public/Granted literature
- US20080248616A1 Integration of strained Ge into advanced CMOS technology Public/Granted day:2008-10-09
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