Invention Grant
- Patent Title: Gate sidewall spacer and method of manufacture therefor
- Patent Title (中): 门侧壁间隔件及其制造方法
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Application No.: US11173088Application Date: 2005-07-01
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Publication No.: US07790561B2Publication Date: 2010-09-07
- Inventor: Richard P. Rouse , Shashank S. Ekbote , Haowen Bu
- Applicant: Richard P. Rouse , Shashank S. Ekbote , Haowen Bu
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent John J. Patti; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L21/336
- IPC: H01L21/336
Abstract:
The present invention provides a method for manufacturing a semiconductor device, a semiconductor device, and a method for manufacturing an integrated circuit including a semiconductor device. The method for manufacturing the semiconductor device, without limitation, may include providing a gate dielectric layer (413, 423) and a gate electrode layer (418, 428) over a substrate (310), and forming a gate sidewall spacer (610, 630) along one or more sidewalls of the gate dielectric layer (413, 423) and the gate electrode layer (418, 428) using a plasma enhanced chemical vapor deposition process, and forming different hydrogen concentration in NMOS and PMOS sidewall spacers (610, 630) using a local hydrogen treatment (LHT) method.
Public/Granted literature
- US20070004156A1 Novel gate sidewall spacer and method of manufacture therefor Public/Granted day:2007-01-04
Information query
IPC分类:
