Invention Grant
- Patent Title: Method for FEOL and BEOL wiring
- Patent Title (中): FEOL和BEOL接线方法
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Application No.: US11749898Application Date: 2007-05-17
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Publication No.: US07790611B2Publication Date: 2010-09-07
- Inventor: Brent A. Anderson , John J. Ellis-Monaghan , Edward J. Nowak , Jed H. Rankin
- Applicant: Brent A. Anderson , John J. Ellis-Monaghan , Edward J. Nowak , Jed H. Rankin
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Richard M. Kotulak, Esq.
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
A method for forming a conductive structure of sub-lithographic dimension suitable for FEOL and BEOL semiconductor fabrication applications. The method includes forming a topographic feature of silicon-containing material on a substrate; forming a dielectric cap on the topographic feature; applying a mask structure to expose a pattern on a sidewall of the topographic feature, the exposed pattern corresponding to a conductive structure to be formed; depositing a metal at the exposed portions of the sidewall and forming one or more metal silicide conductive structures at the exposed sidewall portions; removing the dielectric cap layer; and removing the silicon-containing topographic feature. The result is the formation of one or more metal silicide conductor structures formed for a single lithographically defined feature. In example embodiments, the formed metal silicide conductive structures have a high aspect ratio, e.g., ranging from 1:1 to 20:1 (height to width dimension).
Public/Granted literature
- US20080284021A1 Method for FEOL and BEOL Wiring Public/Granted day:2008-11-20
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