Invention Grant
US07791388B2 Duty cycle error calculation circuit for a clock generator having a delay locked loop and duty cycle correction circuit 有权
具有延迟锁定环和占空比校正电路的时钟发生器的占空比误差计算电路

  • Patent Title: Duty cycle error calculation circuit for a clock generator having a delay locked loop and duty cycle correction circuit
  • Patent Title (中): 具有延迟锁定环和占空比校正电路的时钟发生器的占空比误差计算电路
  • Application No.: US12203700
    Application Date: 2008-09-03
  • Publication No.: US07791388B2
    Publication Date: 2010-09-07
  • Inventor: Tyler Gomm
  • Applicant: Tyler Gomm
  • Applicant Address: US ID Boise
  • Assignee: Micron Technology, Inc.
  • Current Assignee: Micron Technology, Inc.
  • Current Assignee Address: US ID Boise
  • Agency: Dorsey & Whitney LLP
  • Main IPC: H03K3/17
  • IPC: H03K3/17
Duty cycle error calculation circuit for a clock generator having a delay locked loop and duty cycle correction circuit
Abstract:
A system and method for generating a correction signal for correcting duty cycle error of a first clock signal relative to a second complementary clock signal. Changes to a time difference between high- and low-portions of the first clock signal are detected and the correction signal is generated in response to and accordance with the detected changes.
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