Invention Grant
- Patent Title: State retaining power gated latch and method therefor
- Patent Title (中): 国家保留电源闸门及其方法
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Application No.: US12022193Application Date: 2008-01-30
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Publication No.: US07791389B2Publication Date: 2010-09-07
- Inventor: Scott I. Remington
- Applicant: Scott I. Remington
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Daniel D. Hill; James L. Clingan, Jr.
- Main IPC: H03K3/356
- IPC: H03K3/356

Abstract:
A circuit has first latch, a second latch, a coupling circuit, and a power down circuit. The first latch has an input/output coupled to a data node. The second latch has an input/output. The coupling circuit is coupled between the input/output of the second latch and the data node. The coupling circuit is enabled during a normal operation of the circuit and disabled during a power down mode of the circuit. The power down control circuit is for disabling the first latch during the power down mode and for a time period after a transition from the power down mode to the normal operation. This allows the second latch to set the state of the first latch when transitioning from the power down mode to the normal mode. Thus normal operation can be fast, and the power down mode can have low leakage current.
Public/Granted literature
- US20090189664A1 STATE RETAINING POWER GATED LATCH AND METHOD THEREFOR Public/Granted day:2009-07-30
Information query
IPC分类: