Invention Grant
US07791919B2 Semiconductor memory device capable of identifying a plurality of memory chips stacked in the same package
失效
半导体存储器件能够识别堆叠在相同封装中的多个存储器芯片
- Patent Title: Semiconductor memory device capable of identifying a plurality of memory chips stacked in the same package
- Patent Title (中): 半导体存储器件能够识别堆叠在相同封装中的多个存储器芯片
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Application No.: US12270292Application Date: 2008-11-13
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Publication No.: US07791919B2Publication Date: 2010-09-07
- Inventor: Yuui Shimizu
- Applicant: Yuui Shimizu
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2007-303307 20071122
- Main IPC: G11C5/04
- IPC: G11C5/04

Abstract:
A semiconductor memory device is configured to vertically stack a plurality of memory chips using a resistance-change memory element as a memory cell in one package. The memory chips each have first and second memory position detection pads connected via chip top and bottom electrodes facing each other. Of the vertically stacked memory chips, the lowermost memory chip is provided with the connected chip bottom electrodes of the first and second memory position detection pads. The memory chips each control the variable resistance element, and in a state that the first memory position detection pad has a higher resistance than the second memory position detection pad, compare a voltage applied to the first memory position detection pad with the chip position detection signal using the comparator when a voltage is applied between the first and second memory position detection pads provided on the uppermost layer memory chip.
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