An SEU hardening circuit and method is disclosed. In one embodiment, a method includes providing a semiconductor memory component having a pair of pMOS transistors and a pair of nMOS transistors, tying a first pMOS body terminal of a first pMOS transistor of the pair of pMOS transistors to a second pMOS gate terminal of a second pMOS transistor of the pair of pMOS transistors, and tying at least a first pre-designated body terminal of at least one transistor selected from the group including essentially of a pair of pMOS transistors and a pair of nMOS transistors to at least a second pre-designated terminal of at least one pre-designated transistor selected from the group including essentially of the pair of pMOS transistors and the pair of nMOS transistors.