Invention Grant
- Patent Title: Nonvolatile semiconductor memory device
- Patent Title (中): 非易失性半导体存储器件
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Application No.: US12571917Application Date: 2009-10-01
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Publication No.: US07791943B2Publication Date: 2010-09-07
- Inventor: Motoharu Ishii , Seiichi Endo
- Applicant: Motoharu Ishii , Seiichi Endo
- Applicant Address: JP Tokyo
- Assignee: Renesas Technology Corp.
- Current Assignee: Renesas Technology Corp.
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2005-132441 20050428
- Main IPC: G11C11/34
- IPC: G11C11/34

Abstract:
In a nonvolatile memory cell, a selection transistor is connected to a memory cell transistor in series. The selection transistor is formed into a double layer gate structure, and has a voltage of each gate driven individually and separately. Using capacitive coupling between these stacked gate electrode layers of the selection transistor, a gate potential of the selection transistor is set to the predetermined voltage level. An absolute value of the voltage level generated by a voltage generator to the gates of the selection transistor can be made small, so that current consumption can be reduced and an layout area of the voltage generator can be reduced. Thus, a nonvolatile semiconductor memory device with a low current consumption and a small chip layout area is provided.
Public/Granted literature
- US20100014355A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2010-01-21
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