Invention Grant
- Patent Title: Memory device architectures and operation
- Patent Title (中): 内存设备架构和操作
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Application No.: US11699954Application Date: 2007-01-30
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Publication No.: US07791952B2Publication Date: 2010-09-07
- Inventor: Frankie F. Roohparvar
- Applicant: Frankie F. Roohparvar
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Leffert Jay & Polglaze, P.A.
- Main IPC: G11C16/04
- IPC: G11C16/04

Abstract:
Non-volatile memory devices logically organized to have erase blocks of at least two different sizes provide for concurrent erasure of multiple physical blocks of memory cells, while providing for individual selection of those physical blocks for read and program operations. In this manner, data expected to require frequent updating can be stored in locations corresponding to first erase blocks having a first size while data expected to require relatively infrequent updating can be stored in locations corresponding to second erase blocks larger than the first erase blocks. Storing data expected to require relatively more frequent updating in smaller logical memory blocks facilitates a reduction in unnecessary erasing of memory cells. In addition, by providing for larger logical memory blocks for storing data expected to require relatively less frequent updating, efficiencies can be obtained in erasing larger quantities of memory cells concurrently.
Public/Granted literature
- US20080183950A1 Memory device architectures and operation Public/Granted day:2008-07-31
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