Invention Grant
- Patent Title: Design structure of implementing power savings during addressing of DRAM architectures
- Patent Title (中): 在DRAM架构寻址期间实现节能的设计结构
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Application No.: US12024443Application Date: 2008-02-01
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Publication No.: US07791978B2Publication Date: 2010-09-07
- Inventor: Gerald K. Bartley , Darryl J. Becker , John M. Borkenhagen , Philip R. Germann , William P Hovis
- Applicant: Gerald K. Bartley , Darryl J. Becker , John M. Borkenhagen , Philip R. Germann , William P Hovis
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn, LLP
- Main IPC: G11C8/00
- IPC: G11C8/00

Abstract:
A design structure embodied in a machine readable medium used in a design process includes random access memory device having an array of individual memory cells arranged into rows and columns, each memory cell having an access device associated therewith. Each row of the array further includes a plurality of N word lines associated therewith, with a wherein N corresponds to a number of independently accessible partitions of the array, wherein each access device in a given row is coupled to only one of the N word lines of the row. Logic in signal communication with the array receives a plurality of row address bits and determine, for a requested row identified by the row address bits, which of the N partitions within the requested row are to be accessed, such that access devices within a selected row, but not within a partition to be accessed, are not activated.
Public/Granted literature
- US20090196118A1 Design Structure Of Implementing Power Savings During Addressing Of DRAM Architectures Public/Granted day:2009-08-06
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