The invention is provided to improve the information processing efficiency of a multiprocessor system. An information processing apparatus 1000 comprises a main processor 200 for exercising centralized control on the entire apparatus, a graphic processor 100 for performing image processing operations, and a main memory 50. The information processing apparatus 1000 also comprises a DMA controller 28 which controls m (m is an integer, m>1) pieces of data transfer simultaneously, a main memory 50 for data intended for the particular processing is expanded first, and a group of n (n is an integer, n>m) buffers 12 for storing data when the data is transferred from the main memory 50. When a plurality of data transfers are performed simultaneously, a first buffer out of the group of buffers 12 is set as the destination of one of the data transfers, and a second buffer is set as the destination of another data transfer.