Invention Grant
US07793025B2 Hardware managed context sensitive interrupt priority level control
有权
硬件管理上下文敏感中断优先级控制
- Patent Title: Hardware managed context sensitive interrupt priority level control
- Patent Title (中): 硬件管理上下文敏感中断优先级控制
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Application No.: US12057989Application Date: 2008-03-28
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Publication No.: US07793025B2Publication Date: 2010-09-07
- Inventor: Robert Ehrlich , Brett W. Murdock , Craig D. Shaw
- Applicant: Robert Ehrlich , Brett W. Murdock , Craig D. Shaw
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agency: Hamilton & Terrile, LLP
- Agent Michael Rocco Cannatti
- Main IPC: G06F13/14
- IPC: G06F13/14 ; G06F13/26

Abstract:
A flexible interrupt controller circuit and methodology are provided which use an interrupt circuit (300) that multiplexes (324) a plurality of interrupt priority registers (321, 322) based on the current context of the system that is identified in mode control selector (326). By using the mode control selector (326) to selectively couple different priority level assignments to a priority encoding module (330), context sensitive switching of the priority levels assigned to each interrupt request can be implemented with reduced latency. The context switch could be based on an OS context ID, power management modes, security modes, and other system defined modes where priority levels would differ. The selected priority level information is used to provide an interrupt request signal (332) which will cause an interrupt to occur in the data processing system.
Public/Granted literature
- US20090248935A1 Hardware Managed Context Sensitive Interrupt Priority Level Control Public/Granted day:2009-10-01
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