Invention Grant
US07793072B2 Vector execution unit to process a vector instruction by executing a first operation on a first set of operands and a second operation on a second set of operands
有权
矢量执行单元，通过对第一组操作数执行第一操作和对第二组操作数执行第二操作来处理向量指令
- Patent Title: Vector execution unit to process a vector instruction by executing a first operation on a first set of operands and a second operation on a second set of operands
- Patent Title (中): 矢量执行单元，通过对第一组操作数执行第一操作和对第二组操作数执行第二操作来处理向量指令
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Application No.: US10699571Application Date: 2003-10-31
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Publication No.: US07793072B2Publication Date: 2010-09-07
- Inventor: Kenneth Dockser
- Applicant: Kenneth Dockser
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Dillon & Yudell LLP
- Main IPC: G06F15/82
- IPC: G06F15/82
Abstract:
A microprocessor including an execution unit enabled to execute an asymmetric instruction, where the asymmetric instruction includes a set of operand fields and an operation code (opcode). The execution unit is configured to interpret the opcode to perform a first operation on a first set of data indicated by the set of operand fields and to perform a second operation on a second set of data indicated by the set of operand fields, wherein the set of operand fields indicate different sets of data with respect to the first and second operations and further wherein the first and second operations are mathematically different.
Public/Granted literature
- US20050097299A1 Processor with asymmetric SIMD functionality Public/Granted day:2005-05-05
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