Invention Grant
US07793083B2 Processor and system for selectively disabling secure data on a switch
有权
处理器和系统,用于选择性地禁用交换机上的安全数据
- Patent Title: Processor and system for selectively disabling secure data on a switch
- Patent Title (中): 处理器和系统,用于选择性地禁用交换机上的安全数据
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Application No.: US11667762Application Date: 2005-11-24
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Publication No.: US07793083B2Publication Date: 2010-09-07
- Inventor: Masaaki Harada , Tsutomu Sekibe
- Applicant: Masaaki Harada , Tsutomu Sekibe
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Wenderoth, Lind & Ponack, L.L.P.
- Priority: JP2004-342197 20041126
- International Application: PCT/JP2005/021614 WO 20051124
- International Announcement: WO2006/057316 WO 20060601
- Main IPC: G06F7/38
- IPC: G06F7/38 ; G06F9/00 ; G06F9/44 ; G06F15/00

Abstract:
A processor (10) manages, in an instruction management unit (103) and a data attribute management unit (105), secure attributes indicating whether instruction code and data stored in an instruction cache (102) and a data cache (104) of the processor (10) are confidential information. When the instruction code and the data are confidential information, the processor (10) also manages secure processing identification information for indicating in which secure process the confidential information is to be used. When the operating mode is switched from the secure mode to the normal mode, only the confidential information is disabled by a memory disabling unit (108). This prevents confidential information from being analyzed by the processor in the normal mode.
Public/Granted literature
- US20080052534A1 Processor and Secure Processing System Public/Granted day:2008-02-28
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