Invention Grant
- Patent Title: Flash anneal for a PAI, NiSi process
- Patent Title (中): 用于PAI,NiSi工艺的闪光退火
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Application No.: US11779187Application Date: 2007-07-17
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Publication No.: US07795119B2Publication Date: 2010-09-14
- Inventor: Chia Ping Lo , Jerry Lai , Chii-Ming Wu , Mei-Yun Wang , Da-Wen Lin
- Applicant: Chia Ping Lo , Jerry Lai , Chii-Ming Wu , Mei-Yun Wang , Da-Wen Lin
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/04
- IPC: H01L21/04

Abstract:
A structure and a method for mitigation of the damage arising in the source/drain region of a MOSFET is presented. A substrate is provided having a gate structure comprising a gate oxide layer and a gate electrode layer, and a source and drain region into which impurity ions have been implanted. A PAI process generates an amorphous layer within the source and drain region. A metal is deposited and is reacted to create a silicide within the amorphous layer, without exacerbating existing defects. Conductivity of the source and drain region is then recovered by flash annealing the substrate.
Public/Granted literature
- US20090020757A1 Flash Anneal for a PAI, NiSi Process Public/Granted day:2009-01-22
Information query
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