Invention Grant
US07795743B2 Wiring substrate having variously sized ball pads, semiconductor package having the wiring substrate, and stack package using the semiconductor package
有权
具有各种尺寸的球垫的布线基板,具有布线基板的半导体封装以及使用该半导体封装的堆叠封装
- Patent Title: Wiring substrate having variously sized ball pads, semiconductor package having the wiring substrate, and stack package using the semiconductor package
- Patent Title (中): 具有各种尺寸的球垫的布线基板,具有布线基板的半导体封装以及使用该半导体封装的堆叠封装
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Application No.: US11539133Application Date: 2006-10-05
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Publication No.: US07795743B2Publication Date: 2010-09-14
- Inventor: Tae-Hun Kim , Hak-Kyoon Byun , Sung-Yong Park , Heung-Kyu Kwon
- Applicant: Tae-Hun Kim , Hak-Kyoon Byun , Sung-Yong Park , Heung-Kyu Kwon
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: Volentine & Whitt, PLLC
- Priority: KR10-2006-0000794 20060104
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
A wiring substrate having variously sized ball pads, a semiconductor package including the wiring substrate, and a stack package using the semiconductor package, to improve board level reliability (BLR) of a semiconductor package or stack package mounted on a mother board are shown. Outer ball pads are formed to have relatively greater surface areas at the corners of the semiconductor package as compared to those at other areas and are formed to have the greatest surface area within a designable range. Additionally, occurrence of cracks may be inhibited at junctions of other solder balls by forming dummy solder pads at the outermost corners among the outer ball pads formed proximate to the corners of the wiring substrate. Stress arising during a board level reliability test is absorbed without product failure at junctions between the dummy solder pads and dummy solder balls.
Public/Granted literature
Information query
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