Invention Grant
- Patent Title: Offset cancellation circuit and display device
- Patent Title (中): 偏移消除电路和显示装置
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Application No.: US12435880Application Date: 2009-05-05
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Publication No.: US07795961B2Publication Date: 2010-09-14
- Inventor: Tomokazu Kojima , Makoto Mizuki
- Applicant: Tomokazu Kojima , Makoto Mizuki
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2008-133150 20080521
- Main IPC: H03F1/02
- IPC: H03F1/02

Abstract:
In an offset cancellation circuit according to the present invention, a first capacitance is connected to a gate of a first transistor of a first active load, and a second capacitance is connected to a gate of a second transistor of the first active load. A switch sets a first time period and a second time period in connection states between the first and second transistors and the first and second capacitances. The connection states between the first and second transistors and the first and second capacitances are set so that a gate voltage of the first transistor is supplied to the first capacitance, and a gate voltage of the second transistor is supplied to the second capacitance during the first time period; and so that the first and second capacitances can retain charges, and the second time period becomes an output time period of the operational amplifier during the second time period.
Public/Granted literature
- US20090289703A1 OFFSET CANCELLATION CIRCUIT AND DISPLAY DEVICE Public/Granted day:2009-11-26
Information query
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