Invention Grant
US07796463B2 Self-feedback control pipeline architecture for memory read path applications
有权
用于存储器读路径应用的自反馈控制流水线架构
- Patent Title: Self-feedback control pipeline architecture for memory read path applications
- Patent Title (中): 用于存储器读路径应用的自反馈控制流水线架构
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Application No.: US12157684Application Date: 2008-06-12
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Publication No.: US07796463B2Publication Date: 2010-09-14
- Inventor: Ming Hung Wang , Jeng-Tzong Shih
- Applicant: Ming Hung Wang , Jeng-Tzong Shih
- Applicant Address: TW Hsin Chu
- Assignee: Etron Technology, Inc.
- Current Assignee: Etron Technology, Inc.
- Current Assignee Address: TW Hsin Chu
- Agency: Saile Ackerman LLC
- Agent Stephen B. Ackerman; Billy Knowles
- Main IPC: G11C8/00
- IPC: G11C8/00

Abstract:
A memory reading apparatus transfers digital data from a memory array that is independent of external clocking rate, where the data transmission time is not limited by the external clock period, and the internal timing of controls permits flexible column selection and no conflicts in the timing between external clock signals and internal bit line sensing ready signal. The memory read apparatus has a data read path circuit and a memory read control apparatus. The data read path circuit is in communication with the memory to acquire the selected data read from the memory, synchronize the selected data, and transfer the selected data from the memory. The memory read control apparatus is in communications with the data read path circuit for selecting the data to be read from the memory, for providing self-feedback signals for synchronizing the selected data for transfer from the memory.
Public/Granted literature
- US20080285363A1 Self-feedback control pipeline architecture for memory read path applications Public/Granted day:2008-11-20
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