Invention Grant
US07796609B2 Packet processing device with load control mechanism based on packet length and CPU time consumption 有权
基于分组长度和CPU时间消耗的具有负载控制机制的分组处理设备

  • Patent Title: Packet processing device with load control mechanism based on packet length and CPU time consumption
  • Patent Title (中): 基于分组长度和CPU时间消耗的具有负载控制机制的分组处理设备
  • Application No.: US11769445
    Application Date: 2007-06-27
  • Publication No.: US07796609B2
    Publication Date: 2010-09-14
  • Inventor: Kouki MieNobuyuki Shima
  • Applicant: Kouki MieNobuyuki Shima
  • Applicant Address: JP Kawasaki
  • Assignee: Fujitsu Limited
  • Current Assignee: Fujitsu Limited
  • Current Assignee Address: JP Kawasaki
  • Agency: Katten Muchin Roseman LLP
  • Priority: JP2006-200358 20060724
  • Main IPC: H04L12/56
  • IPC: H04L12/56
Packet processing device with load control mechanism based on packet length and CPU time consumption
Abstract:
A packet processing device that achieves stable operation by alleviating the workload of packet processing. A packet buffer checks a packet length flag and a processing time flag to observe the device's operating condition for a first connection. When neither of the two flags are on, the packet buffer keeps buffering first packets on the first connection. When either or both flags are on, the packet buffer changes focus to a second connection and begins buffering second packets on the second connection. A packet length monitor turns on the packet length flag if a new cumulative packet length is greater than a packet length threshold. A processing time monitor turns on the processing time flag if a new cumulative processing time estimate is greater than a predetermined processing time threshold.
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