Invention Grant
US07799657B2 Method of fabricating a substrate for a planar, double-gated, transistor process
有权
制造用于平面,双门控晶体管工艺的衬底的方法
- Patent Title: Method of fabricating a substrate for a planar, double-gated, transistor process
- Patent Title (中): 制造用于平面,双门控晶体管工艺的衬底的方法
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Application No.: US12122837Application Date: 2008-05-19
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Publication No.: US07799657B2Publication Date: 2010-09-21
- Inventor: Thuy B. Dao
- Applicant: Thuy B. Dao
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Kim-Marie Vo
- Main IPC: H01L21/46
- IPC: H01L21/46

Abstract:
A semiconductor fabrication process includes forming a sacrificial layer on a substrate of a donor wafer and implanting hydrogen ions into the substrate through the sacrificial layer to create a stress layer in the substrate. After forming the stress layer, multiple layer stacks are formed on the donor wafer substrate including a bottom gate conductor layer and a bottom gate dielectric layer. An upper surface of the donor wafer is bonded to an upper surface of a handle wafer. An oxide or low-k layer may be formed on the handle wafer. A portion of the substrate of the donor wafer is then cleaved. The bottom gate conductor layer is selected from the group including polysilicon, alpha silicon, alpha germanium, W, Ti, Ta, TiN, and TaSiN.
Public/Granted literature
- US20080213973A1 METHOD OF FABRICATING A SUBSTRATE FOR A PLANAR, DOUBLE-GATED, TRANSISTOR PROCESS Public/Granted day:2008-09-04
Information query
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