Invention Grant
US07799667B2 Method for manufacturing semiconductor device with planer gate electrode and trench gate electrode
有权
制造具有平面栅电极和沟槽栅电极的半导体器件的方法
- Patent Title: Method for manufacturing semiconductor device with planer gate electrode and trench gate electrode
- Patent Title (中): 制造具有平面栅电极和沟槽栅电极的半导体器件的方法
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Application No.: US12219008Application Date: 2008-07-15
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Publication No.: US07799667B2Publication Date: 2010-09-21
- Inventor: Satoshi Shiraki , Yoshiaki Nakayama , Shoji Mizuno , Takashi Nakano , Akira Yamada
- Applicant: Satoshi Shiraki , Yoshiaki Nakayama , Shoji Mizuno , Takashi Nakano , Akira Yamada
- Applicant Address: JP Kariya
- Assignee: DENSO CORPORATION
- Current Assignee: DENSO CORPORATION
- Current Assignee Address: JP Kariya
- Agency: Posz Law Group, PLC
- Priority: JP2003-170019 20030613; JP2004-061077 20040304
- Main IPC: H01L21/336
- IPC: H01L21/336
Abstract:
A semiconductor device includes: a semiconductor substrate with a principal plane; a base region disposed on the principal plane; a source region disposed on the principal plane in the base region to be shallower than the base region; a drain region disposed on the principal plane, and spaced to the base region; a trench disposed on the principal plane; a trench gate electrode disposed in the trench through a trench gate insulation film; a planer gate electrode disposed on the principal plane of the semiconductor substrate through a planer gate insulation film; and an impurity diffusion region having high concentration of impurities and disposed in a portion of the base region to be a channel region facing the planer gate electrode.
Public/Granted literature
- US20080293202A1 Method for manufacturing semiconductor device Public/Granted day:2008-11-27
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