Invention Grant
- Patent Title: Semiconductor integrated circuit
- Patent Title (中): 半导体集成电路
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Application No.: US12048837Application Date: 2008-03-14
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Publication No.: US07800140B2Publication Date: 2010-09-21
- Inventor: Kazuyuki Nakanishi , Hidetoshi Nishimura , Tomoaki Ikegami
- Applicant: Kazuyuki Nakanishi , Hidetoshi Nishimura , Tomoaki Ikegami
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2007-068947 20070316
- Main IPC: H01L27/10
- IPC: H01L27/10

Abstract:
A semiconductor integrated circuit is provided which entails no increase in the correction time of OPC and in which non-uniformity in the gate lengths due to the optical proximity effects is surely suppressed. A plurality of standard cells (C1, C2, C3, . . . ), each including gates G extended in the vertical direction, are aligned in the transverse direction to form a standard cell row. A plurality of the standard cell rows are located side by side in the vertical direction to form a standard cell group. Each of the standard cell rows has a terminal standard cell Ce at least one end of the standard cell row. The terminal standard cell Ce includes two or more supplementary gates, each of which is any of a dummy gate and a gate of an inactive transistor.
Public/Granted literature
- US20080224176A1 SEMICONDUCTOR INTEGRATED CIRCUIT Public/Granted day:2008-09-18
Information query
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