Invention Grant
- Patent Title: Power MOS device
- Patent Title (中): 功率MOS器件
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Application No.: US11900603Application Date: 2007-09-11
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Publication No.: US07800169B2Publication Date: 2010-09-21
- Inventor: Anup Bhalla , Sik Lui , Tiesheng Li
- Applicant: Anup Bhalla , Sik Lui , Tiesheng Li
- Applicant Address: BM
- Assignee: Alpha and Omega Semiconductor Incorporated
- Current Assignee: Alpha and Omega Semiconductor Incorporated
- Current Assignee Address: BM
- Agency: Van Pelt, Yi & James LLP
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/94 ; H01L31/062 ; H01L31/113 ; H01L31/119

Abstract:
A semiconductor device comprises a drain, a body disposed over the drain, having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a gate trench extending through the source and the body into the drain, a gate disposed in the gate trench, a source body contact trench having a trench wall and an anti-punch through implant that is disposed along the trench wall. A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a gate trench in the substrate, through the hard mask, depositing gate material in the gate trench, removing the hard mask to leave a gate structure, forming a source body contact trench having a trench wall and forming an anti-punch through implant.
Public/Granted literature
- US20080001219A1 Power MOS device Public/Granted day:2008-01-03
Information query
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