Invention Grant
US07800173B2 Manufacturing process of a vertical-conduction MISFET device with gate dielectric structure having differentiated thickness and vertical-conduction MISFET device thus manufacture
有权
因此制造具有不同厚度的栅极电介质结构和垂直导通MISFET器件的垂直导通MISFET器件的制造工艺
- Patent Title: Manufacturing process of a vertical-conduction MISFET device with gate dielectric structure having differentiated thickness and vertical-conduction MISFET device thus manufacture
- Patent Title (中): 因此制造具有不同厚度的栅极电介质结构和垂直导通MISFET器件的垂直导通MISFET器件的制造工艺
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Application No.: US12074226Application Date: 2008-02-29
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Publication No.: US07800173B2Publication Date: 2010-09-21
- Inventor: Orazio Battiato , Domenico Repici , Fabrizio Marco Di Paola , Giuseppe Arena , Angelo Magri′
- Applicant: Orazio Battiato , Domenico Repici , Fabrizio Marco Di Paola , Giuseppe Arena , Angelo Magri′
- Applicant Address: IT Agrate Brianza
- Assignee: STMicroelectronics, S.r.l.
- Current Assignee: STMicroelectronics, S.r.l.
- Current Assignee Address: IT Agrate Brianza
- Agency: Graybeal Jackson LLP
- Agent Lisa K. Jorgenson; Kevin D. Jablonski
- Priority: ITTO07A0163 20070302
- Main IPC: H01L29/76
- IPC: H01L29/76

Abstract:
According to an embodiment of a method for manufacturing a MISFET device, in a semiconductor wafer, a semiconductor layer is formed, having a first type of conductivity and a first level of doping. A first body region and a second body region, having a second type of conductivity, opposite to the first type of conductivity, and an enriched region, extending between the first and second body regions are formed in the semiconductor layer. The enriched region has the first type of conductivity and a second level of doping, higher than the first level of doping. Moreover, a gate electrode is formed over the enriched region and over part of the first and second body regions, and a dielectric gate structure is formed between the gate electrode and the semiconductor layer, the dielectric gate structure having a larger thickness on the enriched region and a smaller thickness on the first and second body regions. To form the enriched region, a first conductive layer is made on the semiconductor layer, an enrichment opening is formed in the first conductive layer, and a dopant species is introduced into the semiconductor layer through the enrichment opening. Furthermore, the formation of the dielectric gate structure envisages filling the enrichment opening with dielectric material, prior to forming the first body region and the second body region.
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