Invention Grant
- Patent Title: Semiconductor device with crack-resistant multilayer copper wiring
- Patent Title (中): 具有抗裂多层铜线的半导体器件
-
Application No.: US11240645Application Date: 2005-10-03
-
Publication No.: US07800227B2Publication Date: 2010-09-21
- Inventor: Masamichi Kamiyama , Masashi Takase , Takanori Watanabe
- Applicant: Masamichi Kamiyama , Masashi Takase , Takanori Watanabe
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Semiconductor Limited
- Current Assignee: Fujitsu Semiconductor Limited
- Current Assignee Address: JP Yokohama
- Agency: Westerman, Hattori, Daniels & Adrian, LLP
- Priority: JP2004-291895 20041004
- Main IPC: H01L23/522
- IPC: H01L23/522

Abstract:
In a semiconductor device including a multilayer pad, the multilayer pad comprises a first pad layer provided over a semiconductor substrate to have a first copper wiring region and a first intralayer insulating region provided within the first copper wiring region, and a second pad layer provided over the first pad layer via an interlayer insulating film to have a second copper wiring region and a second intralayer insulating region provided within the second copper wiring region. In the semiconductor device, the first copper wiring region, the first intralayer insulating region, the second copper wiring region, and the second intralayer insulating region are provided in the first and second pad layers such that the multilayer pad has a layout in which all the regions are covered with the copper wiring when the multilayer pad is perspectively viewed from a perpendicularly upper direction for the semiconductor substrate.
Public/Granted literature
- US20060097396A1 Semiconductor device Public/Granted day:2006-05-11
Information query
IPC分类: