Invention Grant
US07800350B2 Apparatus for optimizing diode conduction time during a deadtime interval
有权
用于在死区间隔期间优化二极管导通时间的装置
- Patent Title: Apparatus for optimizing diode conduction time during a deadtime interval
- Patent Title (中): 用于在死区间隔期间优化二极管导通时间的装置
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Application No.: US11747360Application Date: 2007-05-11
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Publication No.: US07800350B2Publication Date: 2010-09-21
- Inventor: John M. Pigott
- Applicant: John M. Pigott
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agency: Ingrassia, Fisher & Lorenz, P.C.
- Main IPC: G05F1/40
- IPC: G05F1/40

Abstract:
Deadtime optimization techniques and circuits are provided which implement closed loop feedback to reduce a duration of a deadtime interval by reducing a diode conduction time (DCT) to an optimized or minimized value. Information regarding DCT is fed back to continuously adjust the relative delay between a first driver path which drives a first transistor and a second driver path which drives a second transistor. For instance, information regarding DCT can be measured and stored, and then used to generate a control signal which continuously adjusts (e.g., increases or decreases) a variable delay associated with a delay element in one of the driver paths of one of the transistors. The delay is adjusted to a value which drives the DCT towards an optimum value. By continuously changing the relative delay between the first driver path and the second driver path, the DCT can be driven to an optimum value.
Public/Granted literature
- US20080278125A1 APPARATUS FOR OPTIMIZING DIODE CONDUCTION TIME DURING A DEADTIME INTERVAL Public/Granted day:2008-11-13
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