A voltage level shifter includes a first switch module having a first transistor and a second transistor, each transistor having a drain, a gate, and a source, wherein the drains of the first and the second transistors are coupled to a first voltage terminal. The voltage level shifter further includes a second switch module coupled between the first switch module and a second voltage terminal, the second switch module including at least six transistors coupled each other, wherein each transistor of the second switch module having a gate for receiving a GATE signal, a GATEb signal, a CORE_INPUT signal, a CORE_INPUTb signal, an IO_INPUT signal, or an IO_INPUTb signal, respectively, wherein the second switch module is designed to produce an output signal at an output node in response to the IO_INPUTb signal and the IO_INPUT signal respectively, irrespective of the CORE_INPUTb signal and the CORE_INPUT signal when the GATE signal is logic low, thereby reducing a leakage current flowing from the first voltage terminal to the second voltage terminal.