Invention Grant
US07800943B2 Integrated circuit having a memory cell arrangement and method for reading a memory cell state using a plurality of partial readings 有权
具有存储单元布置的集成电路和使用多个部分读数读取存储单元状态的方法

Integrated circuit having a memory cell arrangement and method for reading a memory cell state using a plurality of partial readings
Abstract:
Embodiments of the invention relate generally to an integrated circuit having a memory cell arrangement and a method for reading a memory cell state using a plurality of partial readings. In an embodiment of the invention, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include at least one memory cell, the memory cell being capable of storing a plurality of memory cell states being distinguishable by a predefined number of memory cell threshold values, and a controller configured to read a memory cell state of the at least one memory cell using a number of reference levels that is higher than the predefined number of memory cell threshold values, wherein the reading includes a first partial reading using a first set of a plurality of reference levels and a second partial reading using a second set of a plurality of reference levels, wherein the second set of a plurality of reference levels includes at least one reference level which is different from the reference levels of the first set of a plurality of reference levels.
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