Invention Grant
US07800959B2 Memory having self-timed bit line boost circuit and method therefor
有权
具有自定时位线升压电路的存储器及其方法
- Patent Title: Memory having self-timed bit line boost circuit and method therefor
- Patent Title (中): 具有自定时位线升压电路的存储器及其方法
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Application No.: US12233922Application Date: 2008-09-19
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Publication No.: US07800959B2Publication Date: 2010-09-21
- Inventor: Lawrence F. Childs , Craig D. Gunderson , Olga R. Lu , James D. Burnett
- Applicant: Lawrence F. Childs , Craig D. Gunderson , Olga R. Lu , James D. Burnett
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Daniel D. Hill; James L. Clingan, Jr.
- Main IPC: G11C16/00
- IPC: G11C16/00

Abstract:
A memory has an array of memory cells, column logic, a write driver, a voltage detector, and a bootstrap circuit. The array of memory cells is coupled to pairs of bit lines and word lines. The column logic is coupled to the array and is for coupling a selected pair of bit lines to a pair of data lines. The write driver is coupled to the pair of data lines. The voltage detector provides an initiate boost signal when a voltage of a first data line of the pair of data lines drops below a first level during the writing of the pair of data lines by the write driver. The bootstrap circuit reduces the voltage of the first data line in response to the boost enable signal. This is particularly beneficial when the number of memory cells on a bit line can vary significantly as in a compiler.
Public/Granted literature
- US20100074032A1 MEMORY HAVING SELF-TIMED BIT LINE BOOST CIRCUIT AND METHOD THEREFOR Public/Granted day:2010-03-25
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