Invention Grant
- Patent Title: Wafer burn-in test circuit
- Patent Title (中): 晶圆老化测试电路
-
Application No.: US12179491Application Date: 2008-07-24
-
Publication No.: US07800964B2Publication Date: 2010-09-21
- Inventor: Youk-Hee Kim , Sun-Mo An
- Applicant: Youk-Hee Kim , Sun-Mo An
- Applicant Address: KR
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR
- Agency: Baker & McKenzie LLP
- Priority: KR10-2007-0081553 20070814
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C29/00

Abstract:
A wafer burn-in test circuit includes an address toggle signal generating unit for generating an address toggle signal in response to address signals having a constant time period, a reset signal generating unit for receiving a wafer burn-in mode activation signal, the address signals, and a reset determination signal among the address signals and then generating a reset signal, a refresh test mode signal generating unit for receiving the address toggle signal and the reset signal and then generating a refresh test mode signal, and a refresh period signal generating unit for receiving the address toggle signal and the refresh test mode signal and then generating a refresh period signal.
Public/Granted literature
- US20090046525A1 WAFER BURN-IN TEST CIRCUIT Public/Granted day:2009-02-19
Information query