A network processor comprises an input interface, an output interface, a switch coupled between the input and output interfaces, and a plurality of processing elements coupled to respective bidirectional ports of the switch. Such processing elements include, in an illustrative embodiment, a scheduler, a security engine, a classification engine, a stream editor, etc. Information associated with a given packet received via the input interface is sequentially processed through multiple ones of the processing elements in a serial processing order based on switching operations of the switch. In the illustrative embodiment, the switch can permit any desired interconnection of the various processing elements so as to achieve a particular packet processing flow appropriate for a given application.