Invention Grant
US07801262B2 All digital phase locked loop architecture for low power cellular applications
有权
用于低功率蜂窝应用的所有数字锁相环体系结构
- Patent Title: All digital phase locked loop architecture for low power cellular applications
- Patent Title (中): 用于低功率蜂窝应用的所有数字锁相环体系结构
-
Application No.: US11551150Application Date: 2006-10-19
-
Publication No.: US07801262B2Publication Date: 2010-09-21
- Inventor: John Wallberg , Robert B. Staszewski
- Applicant: John Wallberg , Robert B. Staszewski
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H03D3/24
- IPC: H03D3/24

Abstract:
A novel mechanism that is operative to observe and compare the differentiated phase of the reference and variable PLL loop signals using a frequency detector. The resultant phase differentiated error is then accumulated to yield the phase error. The operation of the loop with the frequency detector is mathematically equivalent to that of the phase detector. A frequency error accumulator is used to generate the integral of the frequency error. The frequency error accumulator also enables stopping the accumulation of the frequency upon detection of a sufficiently large perturbation, effectively freezing the operation of the loop as subsequent frequency error updates are not accumulated. Upon removal of the phase freeze event, accumulation of the frequency error and consequently normal loop operation resumes.
Public/Granted literature
- US20070085579A1 All digital phase locked loop architecture for low power cellular applications Public/Granted day:2007-04-19
Information query
IPC分类: