Invention Grant
US07801701B2 Inserter integrated method and system for logic analyzing error conditions 有权
插件集成方法和系统,用于逻辑分析错误条件

  • Patent Title: Inserter integrated method and system for logic analyzing error conditions
  • Patent Title (中): 插件集成方法和系统,用于逻辑分析错误条件
  • Application No.: US11607411
    Application Date: 2006-12-01
  • Publication No.: US07801701B2
    Publication Date: 2010-09-21
  • Inventor: Paul Mayer
  • Applicant: Paul Mayer
  • Applicant Address: US CT Stamford
  • Assignee: Pitney Bowes Inc.
  • Current Assignee: Pitney Bowes Inc.
  • Current Assignee Address: US CT Stamford
  • Agent Michael J. Cummings; Angelo N. Chaclas
  • Main IPC: G06F19/00
  • IPC: G06F19/00
Inserter integrated method and system for logic analyzing error conditions
Abstract:
An integrated logic analyzer system that provides enhanced troubleshooting capabilities for an inserter machine. The system includes sensors positioned within the inserter machine. A controller is coupled to the sensors, and also provides control signals for operation of the machine. The controller generates error signals upon the occurrence of predetermined instances of sensor signals. A display coupled to the controller indicates machine status based on the signals from the plurality of sensors. An integrated logic analyzer is also coupled to the controller and to the plurality of sensors. The integrated logic analyzer provides a continuous readout of sensor signals from the sensors, and control and status signals from the controller. The controller provides a representation of the continuous readout to the display. In the preferred embodiment, the controller provides a visual representation of individually selectable modules of the inserter system. Machine status, from the controller, is displayed as vertical lines overlaying continuous readout at various points in time. In the preferred embodiments, the integrated logic analyzer further provides a continuous readout of control signals from the controller.
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