Invention Grant
US07801717B2 Method for smart dummy insertion to reduce run time and dummy count
有权
用于智能虚拟插入的方法，以减少运行时间和虚拟计数
- Patent Title: Method for smart dummy insertion to reduce run time and dummy count
- Patent Title (中): 用于智能虚拟插入的方法，以减少运行时间和虚拟计数
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Application No.: US11625658Application Date: 2007-01-22
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Publication No.: US07801717B2Publication Date: 2010-09-21
- Inventor: Gwan Sin Chang , Yi-Kan Cheng , Cliff Hou
- Applicant: Gwan Sin Chang , Yi-Kan Cheng , Cliff Hou
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A method involves providing a circuit pattern, generating a density report for the circuit pattern that identifies a feasible area for dummy insertion, simulating a planarization process with the density report and identifying a hot spot on the circuit pattern, inserting a virtual dummy pattern in the feasible area and adjusting the density report accordingly, and thereafter simulating the planarization process with the adjusted density until the hot spot is eliminated.
Public/Granted literature
- US20080176343A1 Method For Smart Dummy Insertion To Reduce Run Time And Dummy Count Public/Granted day:2008-07-24
Information query
