Invention Grant
US07802162B2 Parity check matrix generation method, data transmission system, encoding device, decoding device, and a parity check matrix generation program
有权
奇偶校验矩阵生成方法,数据传输系统,编码装置,解码装置和奇偶校验矩阵生成程序
- Patent Title: Parity check matrix generation method, data transmission system, encoding device, decoding device, and a parity check matrix generation program
- Patent Title (中): 奇偶校验矩阵生成方法,数据传输系统,编码装置,解码装置和奇偶校验矩阵生成程序
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Application No.: US10586541Application Date: 2005-01-17
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Publication No.: US07802162B2Publication Date: 2010-09-21
- Inventor: Yuzo Senda
- Applicant: Yuzo Senda
- Applicant Address: JP Tokyo
- Assignee: NEC Corporation
- Current Assignee: NEC Corporation
- Current Assignee Address: JP Tokyo
- Agency: Sughrue Mion, PLLC
- Priority: JP2004-011923 20040120
- International Application: PCT/JP2005/000471 WO 20050117
- International Announcement: WO2005/069492 WO 20050728
- Main IPC: H03M13/00
- IPC: H03M13/00

Abstract:
A method that allows the easy generation of low-density parity-check codes that can realize superior error-correcting characteristics. A processor of a transmission line encoder constructs parity check matrix H from partial matrix H1 of m rows and k columns on the left side and partial matrix H2 of m rows and m columns on the right side. The processor generates partial matrix H2 as a unit matrix. The processor generates partial matrix H1 to satisfy the conditions that, when any two rows contained in partial matrix H1 are selected, the two rows have periods that are relatively prime, or when the periods are identical, the two rows have different phases. The processor then joins partial matrix H1 and partial matrix H2 to generate parity check matrix H.
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