Invention Grant
- Patent Title: Layout analysis method and apparatus for semiconductor integrated circuit
- Patent Title (中): 半导体集成电路布局分析方法和装置
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Application No.: US11396660Application Date: 2006-04-04
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Publication No.: US07802218B2Publication Date: 2010-09-21
- Inventor: Yoshio Inoue , Takashi Yoneda , Masaru Ito
- Applicant: Yoshio Inoue , Takashi Yoneda , Masaru Ito
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Semiconductor Limited
- Current Assignee: Fujitsu Semiconductor Limited
- Current Assignee Address: JP Yokohama
- Agency: Staas & Halsey LLP
- Priority: JP2005-323807 20051108
- Main IPC: G06F9/45
- IPC: G06F9/45 ; G06F17/50

Abstract:
A method for analyzing a layout for a semiconductor integrated circuit, which includes a plurality of physical devices, to generate physical parameter distribution enabling accurate recognition of changes in transistor characteristics caused by systematic variations. The method includes holding systematic variation tables for physical parameters dependent on the layout of the semiconductor integrated circuit among physical parameters related to characteristics of the semiconductor integrated circuit, analyzing a design layout pattern of the semiconductor integrated circuit and selecting tables corresponding to the plurality of physical devices, and generating a physical parameter distribution based on the selected tables.
Public/Granted literature
- US20070106967A1 Layout analysis method and apparatus for semiconductor integrated circuit Public/Granted day:2007-05-10
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